Feature/wishbone #38
Feature/wishbone #38
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As the proposed names aren't matching the specification for 100% anymore, I suggest to prefer a clean naming scheme. This isn't chaning the name/meaning itself, just changing abbreviations to full non-abbreviated names.
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| Wishbone/vB3/Wishbone_Generic.vhdl | ||
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| Wishbone/vB3/Wishbone_Generic.vhdl | |
| Wishbone/vB3/Wishbone_Generic.vhdl |
Co-authored-by: Patrick Lehmann <[email protected]>
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Why are names that differ from the Wishbone spec being used? I too do not like shortened names, however, I also cannot see using any names other than the standard names. I see there being some freedom when the interface is a split transaction interface (like AXI) and multiple layers of records are used. |
We decided to adopt full UpperCamelCase names (Cycle, Strobe, Acknowledge, WriteEnable, etc.) instead of the abbreviated spec names. The spec signal names are still documented in comments for reference, so the mapping should be clear to anyone familiar with Wishbone. |
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I solved the conflict for this branch after Avalon was merged.
| WriteEnable : std_ulogic; -- WE_O - Write Enable | ||
| Address : Address_Type; -- ADR_O - Address | ||
| DataOut : Data_Type; -- DAT_O - Data (Master to Slave) | ||
| Select : Select_Type; -- SEL_O - Select |
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Shouldn't it fail for signal Select, because it's a reserved word?
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Interface now uses std_ulogic/std_ulogic_vector, addresses are now unsigned and UpperCamelCase is used to increase readability. Contributions on feature/wishbone are now splitted into a new PR.